WP 7.4: Extreme environments

Contacts:

  • Manuel Rolo, INFN
  • Giulio Borghello, CERN
  • Oscar Augusto De Aguiar Francisco, University of Manchester

Indico link

Project 7.4a: modelling and Development of Cryogenic CMOS PDKs and IP

The project will focus on cryogenic device modelling from selected CMOS technology nodes, the development of ”cold” Process Design Kits (PDKs) and mixed-signal CMOS IP blocks and mixed-signal demonstrator chips for cryogenic operation.

Modern CMOS technologies are qualified down to -40C and, although the extrapolation of the device models down to 77K was verified with VDSM bulk CMOS and FDSOI technology nodes, cold PDKs are fundamental for the development of complex mixed-signal ASICs implementing innovative detector architecture and concepts, data transfer, readout and control. Future Noble Liquid detectors for dark matter searches, neutrino physics, quantum computing interface electronics and quantum sensing will require integrated electronics operating down to the 87K and 4K/100mK temperature ranges, respectively. Some foundries are already working on the development of cryo-capable nodes (e.g. GF 22nm FD-SOI or SkyWater, which offers a 90nm node with cryo-models at 45K-77K-120K-150K) and it is reasonable to assume that the growing interest on the use of CMOS for Quantum Computing and Quantum Sensing could open new opportunities for collaborative efforts with selected silicon foundries on the optimisation of solid-state sensors and CMOS processes for operation at cryogenic temperatures.

The aggregation of the international research team participating to the project will create the critical mass and infrastructures’ network needed to work on device characterisation, development of reliable models and PDK deployment on advanced CMOS for cryogenic temperatures. The project will select the TSMC 28nm as baseline technology node, while for the TSMC 65nm 87K corners will be made available by Fermilab. While the project aims to have the initial involvement of an industrial partner for the cold-PDK design, the availability of new funding and resources will allow to create infrastructures, tools and competences for in-house cold-PDK development. The potential applications of these IP blocks and design framework include photon detection in Liquid Argon and Liquid Xenon experiments for astroparticle physics, and CMOS interface circuitry for quantum computing and sensing. Consequently, the project will explore temperature corners spanning from 165K-87K down to 4K.

The design teams will, in parallel, develop core mixed-signal IPs optimised for low-temperature operation, such as ADCs, TDCs, DACs, LVDS transceivers, SPI, bandgaps and power management circuits. The project will also support the characterisation, documentation and git repository of such Cold-IP Library. The design groups will work on the development of a small-scale (MPW) cold demonstrator single-photon detector chip for fast timing applications implementing a low-power and scalable architecture. The use of a digital-on-top integration flow on such a multi-channel mixed-signal IC will allow or the demonstration of the cold-PDK capabilities for the implementation of system-ready complex designs.

Contributors: TU Graz (AT), University of Sherbrooke (CA), FZJ (DE), INFN (IT), KEK (JP), ICCUB (ES), EPFL (CH), RHUL (UK), University of Oxford (UK), Fermilab (US)

Project contact person: Manuel Rolo, INFN

Project 7.4b: Radiation Resistance of Advanced CMOS Nodes

This project investigates the radiation response of CMOS technologies from the 28nm node onward for use in the next generations of ASICs for particle detectors.

CMOS technology has long served as the foundation for electronic devices used in both commercial and scientific applications. The performance of MOS transistors generally improves as feature size is reduced, leading to continuous efforts to miniaturize the technology and devices. The benefits of scaling have led CERN to move from the 250nm technology node used for the Application Specific Integrated Circuits (ASICs) installed in the particle detectors of the LHC, to the 130nm and 65nm CMOS technologies used for the HL-LHC, and more recently to the 28nm technology for post-LS4 projects. Although scaling brings performance benefits, the sensitivity of CMOS technology to radiation effects does not necessarily improve with advanced nodes. As ASICs for future detector will continue to be based on CMOS technology, it is imperative to assess the radiation hardness of advanced nodes. The evaluation of the radiation sensitivity of a technology node may require multiple years and it is a multi-perspective process that benefits from a collaborative effort across several institutes.

  1. prototyping test chips in 28nm CMOS technology,
  2. radiation tests in 28nm CMOS technology,
  3. prototyping test chips in FinFET technology,
  4. radiation tests in FinFET technology.

Contributors: CERN (CH), TU Graz (AT), INFN Pavia (IT), Uni. Bergamo (IT), Uni. Padova (IT), Uni. Pavia (IT), CPPM (FR)

Project contact person: Giulio Borghello, CERN

Project 7.4c: Cooling and cooling plates

This project focuses on the development of the next generation of cooling plates for front-end electronics and sensors based on different materials/techniques. The main goal is to explore manufacturing techniques while improving electronics integration with a cost-effective solution. This project groups different topics covered by different collaborations which will be presented in the coming sections.

Micro-channel cooling plates are extremely efficient in removing the heat from the front-end electronics and/or sensors since the coolant is very close to the heat source. This project aims to improve its integration and cost, and also explore alternative base materials while minimizing its material budget, increasing its ability to dissipate more power and integrating more electronics features. The optimization of those aspects is extremely application-dependent. The topics covered by different collaborations are presented below:

  • Silicon microchannels via buried channels (T1) → this topic has two work lines: On one hand, the development of “active interposers” which hold the mechanical support and the embedded micro-channels to provide the local, high-efficient cooling, together with a re-distribution metal layer (RDL) that can provide the interconnection of the assembly of detector plus front-end electronics with the back-end electronics and the rest of the system. On the other hand, the work to obtain a microchannel technology fully compatible with the (CMOS) sensors in the same substrate.

  • Silicon microchannels via thermo-compression (T2) this topic covers several developments carried by a collaboration of French laboratories: 1) the setting up of a dedicated cooling test bench; 2) the fabrication of cooling plates with icro-channels of various geometrical and surface form factors; 3) the development of numerical 3D models - based on dedicated measurements - and their implementation in numerical simulation tools to optimize the micro-channel heat exchanger design; 4) the development a low-cost silicon cooling-plates fabrication process, mainly based on an innovative bonding technique: “the hyperbaric bonding”, which uses thin layer of gold - similarly to the thermo-compression - and is performed at room temperature inside an hyperbaric chamber; 5) the developments of cooling-plates interconnects to allow the fabrication of heat exchangers covering large areas.

  • Ceramics substrate (T3) → This topic covers the investigation of ceramics cooling plates with embedded microchannels and additional electronic features. Low-temperature cofiring ceramic (LTCC) and high-temperature cofiring ceramic (HTCC) combine different ceramic layers to enclose the channels and it offers the possibility to integrate high conductivity materials in between those layers as well. Lines inside the cooling plate can be accessed via vias. The benchmark model for the characterization of those structures will be the LHCb VELO Upgrade 2 which has very challenging requirements (high power density, high pressure, and in vacuum operation).

  • 3D printing (T4) → The ability to print cooling/mechanical structures brings a higher level of design flexibility, fast turn-around processing time, and cost-effectiveness, especially in electronics-dense areas with limited space. In this scenario, titanium 3D printing via selective laser sintering will be explored in this topic. The surface finishing and potential of the material budget will be improved by exploring in addition post-processing techniques. This topic will also follow the requirements for the LHCb VELO Upgrade 2 (CO2 ) as a benchmark but a similar approach can also be used for different applications.

Contributors: University of Sherbrooke (CA), CERN (CH), DESY (DE), IMB-CNM (ES), IFIC Valencia (ES), University of Manchester (UK), LAPP (FR), LEGI (FR),LPNHE (FR), LPSC (FR), CPPM (FR)

Project contact person: Oscar Augusto De Aguiar Francisco, University of Manchester