WP 7.2: Intelligence on the detector

Contacts:

  • Kostas Kloukinas, CERN
  • Levi Marien, KU Leuven
  • Davide Ceresa, CERN
  • Maciej Kachel, IPHC

Indico link

Project 7.2a: e-FPGA

Not yet ready to be launched !

Project 7.2b: Radiation Tolerant RISC-V System-On-Chip

The project aims to develop a radiation-hardened System-On-Chip (SoC) based on the RISC-V ISA standard.

The development of a radiation-tolerant RISC-V SoC is a cutting-edge project aimed at creating a reliable and resilient central processing unit (CPU) for High Energy Physics applications. This SoC will be based on the open-source RISC-V architecture and designed to withstand the adverse effects of ionizing radiation, which can cause soft errors in electronic components. The project can be divided into different topics:

  1. SoC architectures: Defining the specifications for a RISC-V SoC involves documenting the key characteristics, capabilities, and requirements that the processor should meet. These specifications serve as a reference for the design and development process. They should include at least RISC-V ISA variant (e.g., RV32I, RV64G), instruction set and operations, word size and addressing, number of registers, pipeline depth, and memory hierarchy. The project might also propose to pursue more than one set of specifications to satisfy different applications.

  2. Radiation Tolerance design methodology: Developing a radiation-tolerant RISC-V SoC requires a robust methodology to ensure the processor can operate reliably in high-radiation environments. Several techniques are available to mitigate radiation-induced errors, from triple modular redundancy (TMR), spatial and temporal redundancy, and built-in self-repair mechanisms. In addition, Radiation-Hardened components, such as memories, register’s bank and interconnects, must be designed and integrated into the system.

  3. Verification methodology: Proper verification of a CPU design and associated instruction set architecture (ISA) is one of the most challenging activities that a CPU core engineering group must tackle. Adding a radiation tolerance feature, the verification methodologies must ensure the processor’s functionality and robustness in the face of ionizing radiation.

  4. SoC generator toolchain: System-on-Chip (SoC) generation tools are software applications and frameworks that facilitate the design, development, and testing of SoCs. These tools play a critical role in the process of creating complex integrated circuits that incorporate multiple hardware and software components into a single chip. SoC generation tools support various stages of SoC development, including design, verification, synthesis, simulation, and integration.

Contributors: FH Dortmund (DE), KU Leuven (BE), CERN (CH), UKRI-STFC RAL (UK), Royal Holloway University Of London (UK), University of Warwick (UK), University of Bristol (UK), Fermilab (US)

Project contact persons: Kostas Kloukinas, CERN and Levi Marien, KU Leuven

Project 7.2c: Virtual Electronic System Prototyping

The project aims to develop a simulation of the readout chain of a particle detector at a high level, modeling the essential components and processes that occur from the moment particles interact with the detector to the digital readout of the collected data.

Simulating the readout chain in a High Energy Physics (HEP) detector at a high level involves modeling the essential components and processes that occur from when particles interact with the detector to the digital readout of the collected data.

The project can be divided into different topics:

  1. Signal generation in detector elements (before conditioning and processing): Simulate the detector physics using specialized tools (e.g. Sentaurus TCAD). Geometry and energy deposition data (obtained by Monte Carlo techniques) are required as input from particle physics simulation teams. In simple cases the signal generation can be also provided by these teams, however the lack of proper modelling of semiconductor physics in standard tools (e.g. GEANT4, Allpix2) may require the use of TCAD software.

  2. Digitization and Signal Processing: Simulate the readout electronics that collect signals from the detector elements. This includes pre-amplifiers, shaping amplifiers, analog-to-digital converters (ADCs), and other electronics components. Model the noise and electronics response characteristics such as gain, shaping time, and filtering. Digitize the continuous signals into discrete digital samples.

  3. Data readout architecture: Simulate the readout architecture and data acquisition system that collects, stores, and transmits data from the detector to a computing facility for analysis. Implement a trigger system that decides whether an event should be recorded based on criteria like transverse energy, missing energy, or specific particle signatures. In addition to the development topics listed above, the project provides a USER role that can use the toolchain to model and simulate any detector during the development phase for debugging and refining the framework.

Contributors: CERN (CH), IPHC (FR)

Project contact persons: Davide Ceresa, CERN and Maciej Kachel, IPHC